IP-cores for FPGA & ASIC

NEW RELEASE! LEARN MORE HERE

TICO-RAW is the new RAW !

intoPIX TICO-RAW is a revolutionary RAW (Bayer) image processing and compression technology, extremely tiny and low power.


intoPIX has developped various architectures running at different pixel per clock to target a wide range of pixel rates/ frame rates/ image sensors resolutions and a wide range of FPGA devices & ASIC technology nodes. Encoding or Decoding can be achieved into the small Xilinx & Intel FPGAs, robust for real-time operation with no latency. intoPIX offers silicon-proven IP with very low gate count & SRAM consumption in ASICs.


With such a rapid evolution of available images, image sensors and video resolutions, the need for new ways to handle RAW / image sensor data is bigger than ever before. 


With TICO-RAW, you can capture, transmit, store, edit, preserve, analyze,.. RAW Bayer data "more efficiently" with small bandwidth and file sizes, preserving the full flexibility of "RAW".


Learn more about TICO RAW

IP-cores Features

TICO-RAW IP-cores are fully available and silicon-proven for FPGA and ASIC designs

 Image / Video 
  •  Color space: RAW (CFA-BAYER) - RGGB, RCCB, etc.
    • optional  Monochrome/Greyscale and 4:2:2* modes
  • Bit Depth: 8, 10, 12, 14, 16
  • Resolutions: Any (2Mpx to 160Mpx or more (see example for, HD, 2K, 4K, 8K, 10K hereunder) 
  • Pixel Rate / frame rate*: Any (depending on intoPIX IP-core configuration & targeted device)
TICO-RAW Processing &  Compression
(Latency, Quality, Rate Control)  
  • (Sub) intra-frame : down to 0.1 millisecond
  • Real-time operation guaranteed (no overflow or underflow) 
  • Fixed latency - Only few lines of pixels (number of lines depends on the profile)
  • Adjustable compression ratio down to 1 bit per pixel
  • Support for lossy / visually lossless / near-lossless / mathematically. lossless 
  • CBR (Constant Bit Rate) operation (optional : Constant Quality mode)
FPGA/ASIC Implementation
  • Various Pixel Per Clock architectures available
  •  Low-cost implementation in any FPGAs: very low FPGA logic and internal RAM usage (No external DDR required)
    • Fit in the smallest Xilinx Spartan-6, Artix-7, Kintex-7 , Kintex Ultrascale , Zynq, Virtex Ultrascale, UltrascalePlus, Versal
    • Fit in the smallest Intel Cyclone V, Arria V, Stratix V, Cyclone 10, Arria 10 , Stratix 10
  • Low Gate Area (low gate count / low memory) for ASIC
  • Encoder and decoder have approximately the same complexity 
  • IP-core customizable per application 

* in 422 , the frame rate will be the half of the frame rate achieved in RAW Bayer mode

NEW - HD, 4K, 8K, 10K, 16K RAW and your configuration for FPGA & ASIC 

Based on all the features we are supporting, it is possible to provide custom versions to address your specific needs. 

Contact us for your own configuration. 


See hereunder a list of typical configurations:


IP-CORES
-ENC  / -DEC
 Color
sampling
Sensor
Bit depth
Resolutions examples
Max fps
at 100 MHz*
Max fps
at 250 MHz*
Max fps
 at 300 MHz*
Max fps
at 1 GHz*
 IPX-TICO-RAW-2K
(up to 2048-pixels width)
 RAW CFA Bayer  8, 10, 12, 14, 16
 2048 x 1080
2048 x 2048
 335
177
  839
442
 1006
530
  3354
1769
 IPX-TICO-RAW-4K
(up to 4096-pixels width)
RAW CFA Bayer 8, 10, 12, 14, 16
 4096 x 2160
4096 x 4096 
 84
44
 209
110
 250
132
 837
441
 IPX-TICO-RAW-8K
(up to 8192-pixels width)
RAW CFA Bayer
 8, 10, 12, 14, 16
 7680 x 4000
8192 x 4320
8192 x 8192
24
21
11
60 
52
28
 72
62
33
241 
209
110
ASK FOR YOUR CONFIGURATION 

 * Max Frequency (MHz) of the IP-cores can be adjusted according to your selected pixel per clock architecture and your targeted FPGA or ASIC technology node

Contact us for more information about our TICO-RAW

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Verification code

Resources 

TICO-RAW Solutions overview
Download the product sheet

Related Solutions

TICO RAW Libraries for CPU & GPU

Related News

Read our TICO-RAW blog articles